With the development of the semiconductor technology, the requirements on the performance and feature size of CMOS (Complementary Metal Oxide Semiconductor) devices are increasingly high. For the process integration of 45 nanometers technology node and below, the replacement gate (gate last) process is applied widely. FIG. 1 is a schematic drawing showing a typical conventional gate last process, which includes forming a sacrificial gate 100 first, forming source/drain regions 200, a sidewall spacer 30, and a silicide layer 400 covering the source/drain regions, then removing the sacrificial gate 100 to form an opening 500 surrounded by the inner walls of the sidewall spacer 300, and finally forming a replacement gate stack in the opening. The advantage of such a process is that the replacement gate stack is formed after the formation of the source/drain regions, thereby avoiding the adverse influence on the dielectric and conductor in the gate stack during high temperature annealing and other source/drain manufacturing processes.
However, said process has the following problems: the replacement gate process is complicated and has a high cost; it is more and more difficult to integrate contact holes into a CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor); and it is becoming harder to realize the high-k dielectric/metal gate stack process in a CMOS device. Therefore, it is imperative to develop a new manufacturing process that has the advantages of the replacement gate process while overcoming its problems.